Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide

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ID 721605
Date 2/28/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Intel® SoC EDS 2.3.3. Installing the Development Kit 2.3.4. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board System MAX® 10 with Default Factory Image 3.3.2. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control On-Board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. BTS Test Areas 4.6. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Info Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMCA NRZ Tab 4.2.5.4. The FMCB NRZ Tab 4.2.5.5. The QSFPDD800 PAM4 Tab 4.2.5.6. The MXPM NRZ Tab 4.2.5.7. The MXPM PAM4 Tab 4.2.5.8. The SDI Tab
5. Development Kit Hardware and Configuration x
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG 5.2. Configure the FPGA Device Using the AS Mode (Default Mode) 5.3. Configure the FPGA Device Using the Avalon® -ST Mode 5.4. Daughter Cards
5.4. Daughter Cards x
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. System Management A.2. Power A.3. Clocks A.4. General Input/Output A.5. Memory Interfaces A.6. Communication Interfaces A.7. Daughter Cards A.8. Connectors and Cables
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

4.3. Control On-Board Clock through Clock Controller GUI

The Clock Controller communicates with the system MAX® 10/ Agilex™ 7 device through a 10-pin JTAG header J11 or USB port J10. The system MAX® 10 controls Si5394/Si5391-A/Si5391-B/Si5332, and Agilex™ 7 device controls ZL30733 through the I2C bus.

The instructions to run the Clock Controller GUI are stated in the Running the BTS GUI section. Alternatively, you can start using the Clock Controller feature by selecting the Clock icon on the BTS GUI.

Note: You cannot run the stand-alone Clock Controller GUI application when the BTS or Power Monitor GUI is running at the same time. ZL30733 can be controlled only when a design in which the I2C interface is instantiated, such as the bts_config.sof under the board_test_system\image\ES folder has been downloaded to the FPGA.
Figure 27. Si5394

The following sections describe the Clock Controller GUI buttons.

Read

Reads the current frequency setting for the oscillator associated with the active tab.

Default

Sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board.

Set

Sets the programmable oscillator frequency for the selected clock to the value in the OUTx output controls for Si5394. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Altera recommends resetting the FPGA logic after changing frequencies.

Import

Si5394 has a two-time rewritable non-volatile memory (NVM). You can generate the register list from the Clockbuilder Pro tool and import it into Si5394 to update the settings of the RAM. Register changes are volatile after power cycling.

Figure 28. Si5391-ASimilar control functions with Si5394.
Figure 29. Si5391-BSame with Si5391-A.
Figure 30. Si5332Similar control functions with Si5394. There is no default button for this clock but you can use Import or power cycle the board to get default clock frequencies.
Figure 31. ZL30733Similar control functions with Si5394.

The output frequency of ZL30733 is from 0.5 Hz to 750 MHz. It can generate up to 10 differential outputs with a total of 5 output frequency families.

Import

ZL30733 has a multiple time writable non-volatile memory (NVM). You can generate the register list with the following format:
  • Register Write Command Link: X,<register_address>, <data_bytes>, <register_address> and <data_bytes>, where prefix must be "0x" are in hexadecimal
  • Wait Command Line: W, <time_microseconds>

Import it into ZL30733 to update the RAM settings. Register changes are volatile after power cycling. For more details, refer to ZL30733 on the Microchip website.

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